skill-tree:k:1:2:b
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| skill-tree:k:1:2:b [2020/06/24 17:05] – [Aim] kai_h | skill-tree:k:1:2:b [2025/04/16 18:30] (current) – external edit 127.0.0.1 | ||
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| - | # K1.2-B Hardware Architectures | + | # K1.2 Hardware Architectures |
| - | # Background | + | |
| - | # Aim | + | |
| - | * To provide knowledge about parallel computer architectures, | + | |
| - | between shared and distributed memory systems | + | |
| - | m | + | |
| - | # Outcomes | + | |
| - | * elementary processing elements like CPUs, GPUs, many core architectures | + | |
| - | * vector systems, and FPGAs | + | |
| - | * the NUMA architecture used for symmetric multiprocessing systems where the memory access time depends on the memory location relative to the processor | + | |
| - | * network demands for HPC systems (e.g. high bandwidth and low latency) | + | |
| - | * typical network architectures used for HPC systems, like fast Ethernet (1 or 10 Gbit) or InfiniBand | + | |
| - | # Subskills | + | HPC computer architectures are parallel computer architectures. A parallel computer is built out of |
| + | * Compute units. | ||
| + | * Main memory. | ||
| + | * A high-speed network. | ||
| + | |||
| + | ## Learning Outcomes | ||
| + | |||
| + | * Differentiate different processing elements such as CPU, FPGA, GPU, and others. | ||
| + | * Demonstrate networking with different topologies and interconnects. | ||
| + | |||
| + | ## Subskills | ||
| + | |||
| + | * [[skill-tree: | ||
| + | * [[skill-tree: | ||
skill-tree/k/1/2/b.1593011109.txt.gz · Last modified: 2020/06/24 17:05 by kai_h
