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skill-tree:k:1:2:e

K1.2-E Hardware Architectures

Background

Aim

Outcomes

  • parallelization techniques at the instruction level of a processing element (e.g. pipelining, SIMD processing)
  • advanced instruction sets that improve parallelization (e.g., AVX-512)
  • hybrid approaches, e.g. combining CPUs with GPUs or FPGAs
  • typical network topologies and architectures used for HPC systems, like fat trees based on switched fabrics using e.g. fast Ethernet (1 or 10 Gbit) or InfiniBand
skill-tree/k/1/2/e.txt · Last modified: 2019/08/20 06:29 by 127.0.0.1